Questions & explanations
1. In non-restoring division, after a step where the remainder is negative, what operation do you do in the next step? Show with an example: current remainder -3, divisor 5.
In non-restoring division, when the remainder is negative, the next step adds the divisor instead of subtracting. So if remainder is -3 and divisor is 5, you compute new remainder = (-3) * 2 + 5 = -6 + 5 = -1. Then you shift and continue. The quotient bit for that step is 0 because the remainder after addition is still negative? Actually, the rule: quotient bit = 1 if remainder becomes positive after operation, else 0. But careful: non-restoring uses a different decision. Standard non-restoring: if remainder >= 0, subtract divisor and set quotient bit 1; else add divisor and set quotient bit 0. In this example, remainder -3 (<0), so add divisor: -3+5=2 (positive) → quotient bit 1. Actually typical algorithm: if remainder < 0, add divisor, then quotient bit = 0? Wait, I need to correct. Let me rewrite accurately. In non-restoring, you have a rule: remainder >= 0: subtract, quotient bit 1; remainder < 0: add, quotient bit 0. But then the next step uses the new remainder. So from -3 (<0), add 5 → 2 (positive), then shift left, and next step quotient bit? The algorithm is consistent. For
2. Compare speculative execution in a simple in-order processor versus an out-of-order processor: which has more challenges?
In an in-order processor, speculation is usually just over branches — after fetching a branch, the processor speculatively fetches and executes one path. Instructions still run in order, so tracking speculation is straightforward: if the branch was wrong, everything after it is squashed. Out-of-order processors have more challenges because instructions can execute in any order, and multiple branches may be unresolved at once. For example, a load might execute before a previous branch is resolved, and that load might depend on data from an even older instruction. If that older instruction faults, the load is speculative too. The processor needs a reorder buffer and register renaming to keep results temporary. So out-of-order processors require more complex hardware to ensure precise exceptions.
3. Compare a fully-associative TLB to a set-associative TLB: which is faster and which is more expensive?
A fully-associative TLB allows any translation to be stored in any TLB slot. A set-associative TLB divides the slots into sets, and each translation can only go into one set (e.g., based on the virtual page number). Fully-associative means there are no conflicts — any translation fits anywhere — so the hit rate is theoretically higher. However, checking every TLB entry for a match (content-addressable) is slow and power-hungry, so it is usually small (e.g., 32 entries). Set-associative TLBs use a hash to narrow the search to one set, which is faster and uses less power, allowing larger sizes (e.g., 64 entries, 4-way set-associative). Most modern processors use set-associative TLBs for the data and instruction TLBs, often with a small fully-associative first-level TLB for speed.
4. What is a chiplet design and how does it differ from a monolithic chip?
A chiplet design builds a processor by combining several smaller chips (chiplets) into one package, instead of making one large chip. For example, a CPU might have separate chiplets for cores, memory controller, and graphics. These chiplets are connected using a high-speed link like Infinity Fabric or UCIe. Monolithic chips have all functions on a single piece of silicon. Chiplets can be cheaper to manufacture because smaller chips have higher yield (fewer defects). They also allow mixing different manufacturing processes: a core chiplet might use a cutting-edge process, while an input/output chiplet uses an older, cheaper one. The downside is that communication between chiplets is slower than inside a single chip. Chiplet design is common in modern CPUs from AMD and Intel.
5. Give an example where a speculatively executed load causes a page fault that must be ignored.
Suppose a branch predicts 'taken' and the processor starts executing instructions from the taken path. One of those speculatively executed instructions is a load from memory address X. But address X is not yet in memory — it's on disk, so the memory management unit (MMU) raises a page fault. However, later the branch is resolved as 'not taken', so the load should never have run. The processor must discard the page fault and not let the operating system handle it. Instead, it flushes all speculative work and continues from the correct path. If the processor had allowed the page fault, the OS would ask 'what address?' and find no legitimate reason, possibly crashing or slowing things down. So speculative executions must suppress exceptions until they are confirmed.
6. What is weak ordering (or weak consistency) and why do some architectures use it?
Weak ordering means that the hardware can reorder memory operations freely unless the programmer uses special synchronization instructions. The only guarantee is that synchronizing operations (like lock acquire/release) are ordered. This gives the CPU maximum freedom to optimize performance by reordering and buffering. For example, ARM and PowerPC architectures use weak memory models. The programmer must insert memory barriers (fences) at key points to ensure correct ordering. This makes programming harder because it is easy to write code that works by accident on one model but fails on another. However, it allows very aggressive optimizations that can greatly speed up single-threaded and parallel code. Weak ordering is common in mobile and embedded processors.
7. How does register renaming help in handling a sequence like: R1 = load, R1 = R1+1, R1 = store?
This sequence has three instructions that all write and read R1. Without renaming, the load must finish before the add, and the add before the store — they are serialized by the use of R1. With renaming, the processor assigns three different physical registers to each 'R1' that is written. For example, load writes to P1, add writes to P2, store reads from P2. The load and add can now execute in parallel if the memory address for load is known. The store must wait for the add, but the load does not wait for anything except memory. Renaming removes the false dependency between load and add (they write different physical registers) so the add can start even before the load completes, as long as it uses a different physical register. This speeds up the code.
8. What are the main benefits and challenges of chiplet-based design compared to a single large chip?
The main benefit of chiplets is lower cost and higher yield. Making one large chip is hard because a single defect ruins the whole chip; smaller chiplets have fewer defects per part. Chiplets also allow mixing different technologies; for example, a chiplet for cores can use a new process, while an I/O chiplet uses a mature one. This can save money and improve performance. However, chiplets need fast, energy-efficient connections between them, which can be a bottleneck. The packaging is more complex and requires advanced interposers or bridges. Heat management is also harder because chiplets are close together. Power delivery must be carefully designed. Overall, chiplets are an important trend for scaling performance without huge manufacturing costs.
9. How does a memory fence (barrier) instruction help enforce ordering in weak memory models?
A memory fence (barrier) is an instruction that tells the CPU to guarantee the order of memory operations before and after the fence. For example, a full fence ensures that all reads and writes before the fence are completed before any after it. In weak models, the compiler and CPU can reorder freely without fences. By placing a fence before a critical write (like setting a flag), the programmer ensures that all previous writes are visible to other threads before the flag is seen. Similarly, a fence after reading the flag ensures that subsequent reads see up-to-date data. Fences come in different types: some only order reads, others only writes. They are a necessary tool for writing correct parallel programs on weak memory architectures.
10. What is the role of a silicon interposer in advanced packaging?
A silicon interposer is a piece of silicon that sits underneath multiple chips and connects them electrically. It has many tiny wires that link the chips together, like a bridge. The interposer also has through-silicon vias (TSVs) to connect to the package substrate below. For example, a GPU and its memory stacks might be placed on an interposer to get a wide, fast connection. This allows many parallel wires, giving high bandwidth between chips. The interposer is passive; it does not contain logic, just wires. It helps integrate different types of chips (logic, memory, analog) into one package. Using an interposer reduces the distance signals travel compared to putting chips on a circuit board. It is a key part of 2.5D and 3D packaging.
11. Why might out-of-order execution be less effective in code with many branches?
Out-of-order execution works best when there are many independent instructions that can run in parallel. If the code is full of branches, the processor often does not know which instructions to fetch next until the branch is resolved. While waiting for a branch outcome, the instruction window (the pool of instructions waiting to execute) may shrink because the processor cannot safely fetch past the branch. Even if it speculatively fetches, mispredictions cause flushes that waste the work done. So many branches reduce the number of independent instructions available at once. This limits the out-of-order engine's ability to find parallelism, and performance suffers. Software with long straight-line code (like numeric loops) benefits more.
12. What is sequential consistency and why is it considered simple but slow?
Sequential consistency (SC) means that the result of any parallel program is the same as if all threads' operations were interleaved in some order that respects each thread's program order. In other words, instructions from each thread happen in the order written, and the global order is some interleaving of those. This is easy for programmers to reason about because it matches intuition. However, it prevents many hardware optimizations like out-of-order execution and store buffering. The CPU must wait for memory operations to complete before doing the next one, which slows down programs. Modern CPUs rarely provide full SC because they aim for speed. They offer weaker models and let software add fences to enforce ordering when needed.