China’s CXMT unveils ‘key progress’ on chip structure pursued by Samsung, SK Hynix

CXMT announced key progress on a 4F square memory-cell structure. The design aims to fit more memory cells onto each chip. That could raise storage density while helping the Chinese memory maker compete with Samsung Electronics and SK Hynix.

CXMT plans to use the technology in a new server-memory product. It expects to release a new generation of DDR5 registered dual in-line memory modules, or RDIMMs, by the end of 2026. The module will target enterprise-grade servers rather than ordinary consumer devices.

CXMT has not disclosed detailed specifications or a firm launch date. The company said it had redesigned important manufacturing processes because existing flows could not simply be adapted. It also said the new server product must deliver strong endurance, support continuous operation, tolerate voltage changes, and pass hundreds of compatibility tests.

A 4F square design describes the physical area assigned to one memory cell. Each cell occupies four square F units. The smaller the cell area, the more cells can potentially fit on one chip, making the design important for increasing memory density.

Here, F represents the minimum line width of a semiconductor. It is a basic measure of the smallest patterned feature used in the chip’s manufacturing process. “4F square” therefore describes cell area, not a memory capacity such as gigabytes.

Mainstream commercial DRAM currently uses a 6F square-cell structure, according to the article. Moving to 4F square requires more than shrinking existing patterns. CXMT said its new structure needed redesigned key processes and a proprietary Vertical Surrounding Gate transistor to manage leakage and reduce the cell’s footprint.

The area difference is substantial. A 4F cell occupies four square units, while a mainstream 6F cell occupies six. The 4F design therefore uses two fewer units, or one-third less area than the 6F design.

In a simplified comparison, the same chip area could hold 6 divided by 4, or 1.5 times as many cells. That means up to 50% more cells in the cell-array area, if other design and manufacturing constraints remain equal. More cells can translate into higher memory density.

Real chips also need supporting circuitry, wiring, power systems, and manufacturing margins. The article does not quantify a final capacity increase. It says the 4F structure enables higher storage density and that CXMT’s vertical transistor reduces unit area, helping fit more cells onto a chip.

The technology is not unique to CXMT. Samsung Electronics and SK Hynix, the other leading DRAM producers named in the article, are also pursuing 4F square DRAM. The shift is an industry-wide effort to increase memory density as conventional structures become harder to extend.

SK Hynix unveiled its 4F square roadmap in 2025. Samsung was reported by South Korean media outlet The Elec to be planning mass production of sub-10-nanometre DRAM using the design by 2028. That is a mass-production target, not merely a research milestone.

CXMT plans to roll out a new server-memory product based on the structure by the end of 2026. Its target comes before Samsung’s reported 2028 production date. However, the companies’ announcements are not perfectly identical: CXMT gave a product target, SK Hynix gave a roadmap, and Samsung’s timing concerns mass production.

A denser 4F structure could let server-memory products store more data in less chip area. CXMT plans to apply it to DDR5 RDIMMs for enterprise-grade servers. That could make the technology especially relevant where memory capacity and efficient chip design matter.

Server modules face tougher demands than consumer memory. CXMT said they must support round-the-clock uninterrupted operation and withstand voltage fluctuations. They must also pass hundreds of compatibility tests with processors and motherboards from different manufacturers.

These requirements make reliability and interoperability essential. A consumer product may serve less demanding conditions, but a server module must remain dependable across long operating periods and varied enterprise hardware. CXMT has not disclosed detailed specifications, so the article does not establish the final capacity, endurance rating, or performance of its planned 4F RDIMM.

CXMT says its proprietary Vertical Surrounding Gate, or VSG, transistor is the core of its 4F design. It uses a vertical gate architecture rather than the horizontal transistor-channel arrangement associated with the mainstream 6F structure.

The vertical arrangement changes how the transistor is laid out within the memory cell. CXMT says this architecture addresses current leakage while significantly reducing the unit area. A smaller unit area leaves room for more cells, which supports higher storage density.

The change is fundamental, not a minor adjustment to the existing layout. CXMT said current manufacturing flows could not be adapted to the new structure. It therefore redesigned key processes to optimise the balance between performance and power. The article does not provide detailed electrical measurements for leakage, area reduction, or power consumption.

DRAM stands for dynamic random-access memory. It stores digital data in a large array of tiny memory cells on a semiconductor chip. Each cell represents a bit through an electrical state, while addressing circuits select individual cells for reading or writing.

In general, a DRAM cell combines a transistor with a capacitor. The transistor acts like a switch, controlling access to the cell. The capacitor holds electrical charge that represents data. Because charge gradually leaks away, DRAM needs repeated refreshing to preserve stored information. The article focuses on the cell’s physical structure rather than this operating process.

Smaller transistors and cells allow more of them to fit onto one chip. CXMT’s 4F design reduces the planned cell area compared with mainstream 6F DRAM. Its VSG transistor uses a vertical architecture to address leakage and shrink the unit area, supporting higher density.