Sources: Nvidia asked Samsung, SK Hynix, and Micron to make base dies for its custom NVHBM memory on TSMC's 3nm process; Samsung agreed, its first use of TSMC (Kyu-Seok Shim/Reuters)

Nvidia asked Samsung, SK Hynix, and Micron to manufacture base dies for its custom NVHBM memory. A base die is the foundational chip in a stacked memory package. It connects the memory layers to the outside system and helps manage data movement. The article identifies the request as a manufacturing arrangement involving three major memory companies.

Samsung agreed to make the base dies using Taiwan Semiconductor Manufacturing Company’s 3-nanometre process. This does not mean Samsung will manufacture the entire memory package at TSMC. It means TSMC would produce the base-die component for Nvidia’s design, while Samsung remains involved in the broader memory effort.

The agreement is notable because it would be Samsung’s first use of TSMC. The article does not state whether SK Hynix or Micron accepted Nvidia’s request. It also does not give production volumes, prices, or delivery dates. The confirmed development is Samsung’s decision to use TSMC’s process for Nvidia’s base dies.

NVHBM refers to Nvidia’s custom high-bandwidth memory design. HBM packages place several memory dies vertically in a compact stack. This creates many short data paths and allows much more data to move in parallel than a conventional memory arrangement. The source identifies NVHBM as Nvidia’s custom memory, but does not spell out the acronym.

The base die sits at the bottom of the stack. It provides connections, control logic, and pathways between the stacked memory dies and the package substrate. In simple terms, it acts like a traffic controller and bridge. It helps organize reads and writes, distribute signals, and connect the memory stack to the system using it.

For an AI accelerator, that role matters because calculations constantly request large amounts of data. A capable base die can support efficient communication without requiring separate, long connections to every memory layer. The article specifically says Nvidia asked Samsung, SK Hynix, and Micron to make base dies, but it does not describe NVHBM’s exact internal design.

A 3-nanometre process is a highly advanced manufacturing technology for making logic chips. It can enable dense transistor placement, strong performance, and improved energy efficiency compared with older process generations. Those traits matter in a base die because it must manage many signals inside a compact, high-speed memory package.

The base die controls and connects the stacked memory. Using a modern logic process can give designers more room for interface circuits, control functions, and signal-management features. It may also reduce the energy needed for each operation. These are general benefits of advanced nodes; the article does not state Nvidia’s specific technical reason for choosing TSMC’s 3-nanometre process.

The concrete decision is Samsung’s agreement to use TSMC’s process for Nvidia’s base dies. This separates the manufacturing source for that component from Samsung’s own production operations. It also shows that Nvidia’s custom memory strategy depends on cooperation between companies that normally compete in important parts of the chip industry.

A 3-nanometre process is a modern semiconductor manufacturing generation. It is far more advanced than older nodes such as 14nm, 10nm, or 7nm in the broad industry sequence. Smaller-generation processes generally aim to fit more transistors into a given area while improving performance, power use, or both. The exact advantage depends on the design and the manufacturer.

The “3nm” label is not a precise measurement of one feature across the whole chip. It is a technology name used by a foundry to identify a process generation. Modern process labels no longer map neatly to a single physical transistor dimension. Other measurements, including transistor density, power, speed, and interconnect design, provide a fuller picture of capability.

TSMC’s 3-nanometre process is important here because Nvidia wants base dies made on that advanced platform. The article gives no comparison with a specific older TSMC or Samsung node. It does establish that Samsung agreed to use the process, making this its first use of TSMC.

Samsung agreeing to use TSMC’s process shows that competition and cooperation can occur at the same time. Samsung and TSMC compete in advanced chip manufacturing, yet Samsung may rely on TSMC for a critical component of Nvidia’s custom memory design. The arrangement could help Nvidia combine different companies’ strengths instead of depending on one supplier for every stage.

The mechanism is straightforward. TSMC would manufacture the base dies on its 3-nanometre process, while Samsung remains one of the memory manufacturers Nvidia approached. This creates a link between Samsung’s memory capabilities and TSMC’s manufacturing technology. It also gives TSMC a role in a Samsung-related production effort for Nvidia.

The article confirms Samsung’s agreement and calls it the company’s first use of TSMC. It does not say how long the arrangement will last, whether it will expand, or whether SK Hynix and Micron accepted similar terms. The broader implication is that advanced chip products may increasingly involve partnerships among rivals.

If TSMC cannot supply enough 3nm capacity, Nvidia could look for another foundry with a suitable advanced process. Samsung itself operates chip foundries, so it could potentially manufacture the base dies internally if the design and capacity allowed. Intel Foundry is another possible industry option, although the article does not mention it or confirm qualification for this product.

A second route would be using an older or different process node. That could make production easier, but it might affect power, performance, die size, or design timing. The companies could also divide production among multiple qualified suppliers. Any such change would require engineering work, testing, and manufacturing qualification before high-volume production.

The source confirms only that Nvidia asked Samsung, SK Hynix, and Micron, and that Samsung agreed to use TSMC’s 3nm process. It gives no capacity figures or backup plan. Therefore, these are established industry alternatives, not options confirmed for this specific NVHBM project.

A GPU performs many calculations in parallel, which makes it useful for AI workloads. Those calculations need a constant stream of model weights, activations, and other data. Stacked HBM places memory dies close to the GPU and provides many data connections. This helps supply information quickly without relying only on long, narrow external links.

The base die sits beneath the memory stack. It organizes communication between the memory layers and the package connections leading toward the GPU. Advanced packaging holds the GPU and memory in a tightly coordinated physical arrangement. Together, the short paths, wide interface, and control circuitry allow many bits to move at the same time.

The result is a system designed to reduce data-transfer delays and keep the GPU busy. Nvidia’s request concerns the base dies for its custom NVHBM memory, while TSMC’s 3nm process would manufacture those dies. The article does not provide the package’s bandwidth, layout, or performance figures.