China’s EDA champion buys start-up to address weak link, support Huawei’s Tau Scaling Law

Empyrean Technology is buying a majority stake in Easy-Logic Technology, a Shenzhen start-up founded in 2021. The deal covers 50.38% of the company. Easy-Logic develops logic optimisation tools for chip designers. These tools aim to reduce design iterations and resource use, two important pressures in advanced chip development.

Because the stake is above 50%, Empyrean will control the start-up and consolidate it into its financial statements once the purchase is complete. It will also bring Easy-Logic’s engineering talent and intellectual property into its own business. Empyrean says this will strengthen its next-generation artificial intelligence and three-dimensional integrated circuit design capabilities.

The purchase also supports China’s effort to build domestic alternatives to foreign EDA tools. Easy-Logic’s algorithms have won international competitions, and its products are used by nearly 100 digital chip design firms worldwide. Combining those assets with Empyrean’s existing platforms could help it upgrade tools needed for Huawei’s Tau Scaling Law.

Electronic design automation, or EDA, is software used to design, test and prepare electronic circuits for production. It turns a chip designer’s intended functions into detailed digital descriptions, optimised circuit structures and physical layouts. Verification tools then check whether the design works as intended and can be manufactured.

Its importance grows as chips pack in more transistors and use more advanced manufacturing processes. EDA can optimise logic, reduce resource requirements and shorten repeated design cycles. Empyrean said its AI-optimised tools cut circuit layout work from four weeks to one week. Its Argus platform focuses on physical verification for three-dimensional integrated circuits.

Without capable EDA software, chip designers face longer iterations, greater resource demands and more design risk. The market has long been dominated by Synopsys, Cadence Design Systems and Siemens EDA. China is therefore developing domestic suppliers such as Empyrean, Primarius Technologies and Semitronix as export controls make foreign technology harder to access.

Empyrean will pay 218.8 million yuan for its 50.38% stake in Easy-Logic Technology. The filing gives the deal’s value as about US$33 million. Once completed, the start-up will become part of Empyrean’s consolidated financial statements, showing that the transaction creates a controlled subsidiary rather than a minor investment.

Easy-Logic is small but internationally connected. Founded in 2021, the Shenzhen company develops logic optimisation tools that help chip designers reduce iteration time and resource requirements. Empyrean says the start-up’s algorithms have won international EDA competitions. Its products are already used by nearly 100 digital chip design firms across the globe.

That existing user base gives Empyrean a practical asset alongside Easy-Logic’s engineering talent and intellectual property. The acquisition is intended to strengthen Empyrean’s AI and 3D IC capabilities. It also gives China’s domestic EDA sector another tool supplier as local companies try to narrow the gap with global competitors.

Logic optimisation decides how a circuit’s functions should be arranged so the chip can meet performance, power and resource goals. As manufacturing processes advance, those goals become harder to satisfy. More complex designs create more possible arrangements, while small choices can affect speed, efficiency and whether the final layout fits manufacturing constraints.

Easy-Logic’s tools address this problem by helping designers reduce iteration time and resource requirements. Empyrean says logic optimisation has become increasingly important as the industry advances and adopts Huawei’s Tau Scaling Law. Its AI-optimised software also reduced circuit layout time from four weeks to one week, showing how automation can ease repeated design work.

The issue is not simply drawing a larger or faster chip. EDA software must handle higher performance demands and increasingly complex three-dimensional designs. If domestic tools cannot keep up, Chinese designers may face slower development and greater reliance on foreign software. The acquisition is meant to add talent and algorithms that can strengthen this stage.

US export controls restrict China’s access to advanced technologies, including equipment and tools connected with leading-edge semiconductor development. The article describes these controls as tightening. When foreign technology becomes harder to access, Chinese chip designers need local alternatives that can support design work without depending as heavily on overseas suppliers.

EDA is especially important because microchip development relies on it. The market has long been dominated by Synopsys, Cadence Design Systems and Siemens EDA. Beijing has pressed domestic companies, including Empyrean, Primarius Technologies and Semitronix, to narrow the technological gap with those global rivals.

Empyrean’s purchase of Easy-Logic fits that campaign. It adds domestic algorithms, engineering talent and intellectual property, while strengthening tools for AI and 3D IC design. The pressure is likely to remain high as Huawei’s Tau Scaling Law demands greater performance from EDA software and aims to reduce reliance on cutting-edge lithography equipment blocked by US curbs.

Huawei’s Tau Scaling Law is a chipmaking methodology unveiled earlier this year. Its goal is to achieve transistor performance equivalent to an advanced 1.4-nanometre process node by 2031. The framework is designed to reduce reliance on cutting-edge lithography equipment that US export curbs currently block.

The law changes where performance pressure falls. If designers aim for advanced-node-like transistor performance without relying fully on the newest lithography equipment, they need stronger design methods and software. EDA tools must help optimise logic, manage layouts and verify increasingly demanding chip structures. Empyrean says logic optimisation has therefore become more important.

This creates an opportunity and a challenge for domestic suppliers. Empyrean says Easy-Logic’s talent and intellectual property will strengthen its AI and 3D IC capabilities. Its Argus physical verification platform is described as a key carrier for implementing the Tau Scaling Law. Domestic EDA tools will need to improve substantially to support the 2031 target.

A digital circuit begins as a description of functions, such as logic operations and connections. EDA software converts that idea into a detailed circuit design, then optimises the logic so it meets targets for performance and resource use. Designers next create a physical layout showing where components and connections will sit on the chip.

Verification tools examine whether the logic and physical layout are correct. They check for design problems before manufacturing. In advanced packaging, physical verification also supports three-dimensional integrated circuits. Once the design is ready, lithography uses the layout as a pattern to form structures on semiconductor material through manufacturing steps. Lithography therefore turns the digital plan into physical features.

These stages depend on one another. Better optimisation can improve the layout, while verification confirms that the result is usable. The article says Huawei’s approach seeks advanced-node-like performance while reducing reliance on cutting-edge lithography. That makes capable EDA especially important: software must extract more performance from the available manufacturing process.